Time slot interchange switch with cache

摘要

In accordance with the invention, time slot interchange switches ("TSIS") with a cache memory are described. A time slot interchange switch according to the present invention can include a data memory that receives and stores at least one stream of channel data; a cache memory that receives the at least one stream of channel data; and a microprocessor interface coupled to read data from the cache memory. Accordingly, a method of reading data from a time slot interchange switch to a microprocessor can include writing channel data to a cache memory in addition to a data memory; and providing data from the cache memory in response to requests from a microprocessor interface.