| 摘要 |
Disclosed herein in a dummy pattern structure of a semiconductor device. According to the present invention, the dummy pattern structure comprises daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape, and mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns. Generation of metal residues in a region where metal wirings are not formed when the metal wirings are formed by means of a damascene process are prevented. Also, a delamination phenomenon that interlayer insulating films are fallen apart can be prevented.
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