发明名称 GAME MACHINE
摘要 PROBLEM TO BE SOLVED: To enable the accurate and stable acquisition of the random number values. SOLUTION: In response to the rising edge of the reference clock signal S0, a clock signal generation circuit 172 latches and outputs the signal, fed back from an opposite phase output terminal Q (bar), at a normal phase output terminal Q while inverting the output signal to be outputted from the opposite phase output terminal Q (bar). A counter 173 updates the counts C at the rising timing of the output signal from the normal phase output terminal Q and a latch signal output circuit 174 outputs the latch signal SL at the rising timing of the output signal from the opposite phase output terminal Q (bar). In this manner, a random number generation circuit 17 can make the timing of updating the counts C with the counter 173 different from the timing of outputting the latch signal SL with the latch signal output circuit 174. This enables the accurate and stable acquisition of the random number values in the Pachinko game machines. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005312735(A) 申请公布日期 2005.11.10
申请号 JP20040135463 申请日期 2004.04.30
申请人 SANKYO KK 发明人 UGAWA SHOHACHI;YAMANAKA TAKASHI
分类号 A63F5/04;A63F7/02;(IPC1-7):A63F7/02 主分类号 A63F5/04
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