| 摘要 |
A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*T<SUB>D</SUB>), then clock edges will be generated at a rate that is proportional to the rate of address changes, where T<SUB>D </SUB>is approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.
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