Process for fabricating a dual charge storage location memory cell

摘要

A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer over a semiconductor material layer of a first conductivity type; forming a charge trapping material layer over the first dielectric layer; selectively removing the charge trapping material layer from over a central channel region of the semiconductor material layer, thereby leaving two charge trapping material layer portions at sides of the central channel region; masking the central channel region and selectively implanting dopants of a second conductivity type into the semiconductor material layer to form memory cell source/drain regions at sides of the two charge trapping material layer portions; forming a second dielectric layer over the charge trapping material layer; and forming a polysilicon gate over the second dielectric layer, the polysilicon gate being superimposed over the central channel region and the two charge trapping material layer portions.