| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of measuring correctly delay time differences in the wiring for performance tests. SOLUTION: Because nMOS transistors 141 to 143 are turned off when all the test signals, TCLK, TWE, and TRE are in low level, the electric potential of pads 134 is pulled-up to the constant current source 144. Because the transistor 141 is turned on when the signals TCLK are forced in high level, the electric potential of pads 134 shift to low levels. The time required is measured after the signal TCLK shifts to high levels until the pad 134 shifts to low levels. Similarly, both the times required are measured after the signal TWE shifts to high levels until the pad 134 shifts to low levels, and after the signal TRE sifts to high levels until the pad 134 shifts to low levels. The difference among the measured times are equivalent to the differences of delay times until the signals TCLK, TWE and TRE arrive at the memory macro 110. COPYRIGHT: (C)2006,JPO&NCIPI
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