| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a demultiplexer capable of coping with a bit shift of a comma code while keeping an operating frequency low. <P>SOLUTION: The demultiplexer includes: a serial parallel conversion circuit for received data; a comma detection circuit for detecting coincidence between serial data transferred in parallel and the comma code; a control circuit for extending an activate period of the comma detection section by a prescribed period and providing an output; a state machine whose state transits on the basis of frequency division clock; a recovery clock generating circuit for generating a recovery clock with a period corresponding to the bit length of the received data, receiving an output signal from the control circuit and variably outputting the period of the recovery clock; a delay circuit; a shift register for receiving an output of the delay circuit and converting the output into parallel data; and a latch circuit for receiving an output of the shift register in parallel, sampling the received signal by using the recovery clock and outputting parallel data; and the demultiplexer extends only one period of the recovery clock by a prescribed period in response to the bit shift on the occurrence of the bit shift. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
