发明名称 |
Methods for operating a CPU having an internal data cache |
摘要 |
A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. In this way, a conventional CPU can be operated without read/write access to an external memory in respect of at least part of its memory address space, and therefore with a higher performance resulting from faster memory access and reduced external memory requirements. The CPU 3 may be one of a set of CPU chips 20, 21 in a data processing system, one or more of those chips 20 optionally having read/write access to an external memory 23.
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申请公布号 |
US2005235111(A1) |
申请公布日期 |
2005.10.20 |
申请号 |
US20050523517 |
申请日期 |
2005.02.04 |
申请人 |
KAMIKO TARO;PANDEY PRAMOD |
发明人 |
KAMIKO TARO;PANDEY PRAMOD |
分类号 |
G06F12/00;G06F12/06;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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