发明名称 INTEGRATED CIRCUIT, AND INSPECTION METHOD OF MARGIN DEGREE OF HOLD TIME ERROR
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit and an inspection method of hold margin by which inspection of the hold margin can be performed in a mounting state. SOLUTION: A buffer 100 performs output in normal delay at the time of normal operation, but when hold margin is inspected, output is performed delaying an input clock with delay quantity being larger than the normal delay. An example of delay quantity at the time of inspection is delay of the clock by expected hot carrier. The buffer 100 performs output delaying the clock with delay quantity to which hold margin is added and it is inspected whether data can be taken in normally by F/F101 or not. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005293622(A) 申请公布日期 2005.10.20
申请号 JP20040102540 申请日期 2004.03.31
申请人 NEC ELECTRONICS CORP 发明人 BABA FUJIO
分类号 G01R31/28;G11C29/00;G11C29/56;H03K19/00;(IPC1-7):G11C29/00 主分类号 G01R31/28
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