| 摘要 |
A DLL circuit includes a phase comparator configured to compare timing between a first clock signal and a second clock signal, a delay circuit configured to delay the first clock signal for output as the second clock signal by a delay length responsive to a result of comparison by the phase comparator, and a control circuit configured to suspend supply of the first clock signal to the phase comparator temporarily while the second clock signal is supplied to the phase comparator.
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