SELF-BOOSTING SYSTEM FOR FLASH MEMORY CELLS

摘要

A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero (WLO) immediately adjacent to the source (SGS) or drain side select gate of a NAND flash device (100) to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes.