发明名称 NONVOLATILE SEMICONDUCTOR MEMORY AND ITS MANUFACTURING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory that enables a short-channel transistor and reduces the parasitic capacitance between bit and word lines. <P>SOLUTION: In this embodiment, the semiconductor memory 1 is provided with bit lines 3 formed by injecting n-type impurity into a p-type semiconductor substrate 2 and word lines 5 formed on a semiconductor substrate 1 which are perpendicular to respective bit lines 3. In addition, a charge retention layer 9 is provided below each word line 5 between adjacent two bit lines 3. Each word line is constituted of a control gate lower pattern 11 and control gate upper pattern 13. The control gate lower pattern is formed on the charge retention layer 9. An insulating film 15 is formed on each bit line 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005277183(A) 申请公布日期 2005.10.06
申请号 JP20040089617 申请日期 2004.03.25
申请人 SHARP CORP 发明人 YAMAUCHI YOSHIMITSU
分类号 H01L21/8247;H01L21/8239;H01L21/8246;H01L27/10;H01L27/108;H01L27/112;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
代理机构 代理人
主权项
地址