| 摘要 |
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
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