| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller capable of increasing the apparent speed of a low-speed memory. SOLUTION: The memory controller 10 is interposed between a bus 3 and a memory 4. When there is an access from the bus 3 to a predetermined virtual address space, a virtual memory space control part 13 makes corresponding access to FIFO memories 11, 12 that operate at higher speed than the memory 4 and that have a smaller volume than the memory 4. A DMA controller 14 executes data transfer between the FIFO memories 11, 12 and the memory 4 in asynchronism with the access from the bus 3 to the virtual address space. The head addresses of the destination and the source within the memory 4 and the size of the data to be transferred are preset in the DMA controller 14 by the CPU 2 of the bus 3, etc. COPYRIGHT: (C)2005,JPO&NCIPI
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