| 摘要 |
A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. A first oxide layer overlies the tunnel oxide layer, with an inter poly layer overlying the first oxide layer, and a second poly layer extending over the floating gate transistor region to an edge of the drain implant region.
|
