发明名称 |
High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown |
摘要 |
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.
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申请公布号 |
US6940751(B2) |
申请公布日期 |
2005.09.06 |
申请号 |
US20040765802 |
申请日期 |
2004.01.26 |
申请人 |
KILOPASS TECHNOLOGIES, INC. |
发明人 |
PENG JACK ZEZHONG;FLIESLER MICHAEL DAVID |
分类号 |
G11C17/12;(IPC1-7):G11C11/34 |
主分类号 |
G11C17/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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