发明名称 |
Device and method for detecting alignment of active areas and memory cell structures in dram devices |
摘要 |
A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
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申请公布号 |
US2005184289(A1) |
申请公布日期 |
2005.08.25 |
申请号 |
US20050096836 |
申请日期 |
2005.03.30 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
WU TIE J.;HUANG CHIEN-CHANG;JIANG BO C.;TING YU-WEI;HUANG CHIN-LING |
分类号 |
G11C29/36;H01L21/8242;H01L23/544;H01L27/108;(IPC1-7):H01L21/66;H01L23/58;H01L29/10;H01L21/824 |
主分类号 |
G11C29/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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