发明名称 |
Synchronous mirror delay circuit with adjustable locking range |
摘要 |
A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.
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申请公布号 |
US6933758(B2) |
申请公布日期 |
2005.08.23 |
申请号 |
US20020308453 |
申请日期 |
2002.12.03 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM TAE-HYOUNG;YOON YONG-JIN;KIM NAM-SEOG;LEE KWANG-JIN |
分类号 |
G06F1/12;G06F1/10;H03K5/15;H03L7/081;H03L7/087;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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