| 摘要 |
A mode set entry circuit outputs a latch timing signal at the timing at which the combination of a plurality of commands is detected. A first address latch circuit retains mode designation data for designating the operation mode in response to the latch timing signal and outputs the retained mode designation data. Next, a second address latch circuit retains the mode designation data outputted by the first address latch circuit in response to a latch timing signal indicating the end of the commands in the combination of the plural commands, and outputs the retained mode designation data.
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