发明名称 |
Secure processor arrangement |
摘要 |
A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.
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申请公布号 |
US2005182919(A1) |
申请公布日期 |
2005.08.18 |
申请号 |
US20040020638 |
申请日期 |
2004.12.22 |
申请人 |
STMICROELECTRONICS LIMITED |
发明人 |
DELLOW ANDREW;HOMEWOOD MARK O. |
分类号 |
G06F21/00;G06F21/52;G06F21/71;(IPC1-7):G06F15/00 |
主分类号 |
G06F21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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