| 摘要 |
PROBLEM TO BE SOLVED: To minimize the frequency of plating and reduce the number of interlaminar insulating layers. SOLUTION: The method has a process for forming a resist layer for pattern formation with a prescribed pattern on a substrate wherein an interlayer connection bump is formed, a process for forming a plating film higher than the bump by applying plating all over, a process for forming a resist layer for bump formation on a plating film corresponding to a bump, a process for performing half etching for the plating film by using the resist layer for bump formation as a mask until the resist layer for pattern formation is exposed, a process for forming an insulating layer by burying the bump formed by the half etching, and a process for grinding the insulating layer until the upper edge face of the bump is exposed. A bump and a wiring pattern are formed by half etching at the same time. COPYRIGHT: (C)2005,JPO&NCIPI |
