| 摘要 |
Data on a period longer than the test cycle period concerned in a high-speed pattern test is preset in a period data storage 41 , then a flag 1 is set in a cycle stretch setting part 16 E of a pattern-generation memory 16 at an address position where to execute cycle stretch, then a high-speed pattern test signal is applied, and when the flag 1 is read out by an address from an address counter 14 , a switching part 42 is controlled to switch data read out of a test cycle memory 34 to data set in a setting register 44 for application to a test cycle generator 36 , thereby lengthening the test cycle period.
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