发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an output buffer circuit in which the voltage of an output signal is prevented from oscillating, and a high data read-out rate can be ensured for a recorder when it is provided with the output buffer circuit. SOLUTION: The output buffer circuit 6 comprises a PMOS 2 having a source connected with a power supply terminal VDD and a gate connected with an input terminal 4a, a resistor 11 having one end connected with the drain of the PMOS 2 and the other end connected with the output terminal 5, a resistor 12 having one end connected with the output terminal 5, and an NMOS 3 having a drain connected with the other end of the resistor 12, a gate connected with the input terminal 4b and a source connected with the reference power supply terminal VSS wherein the resistance of the resistor 11 is 2-4 times as high as the equivalent resistance of the PMOS 2 and the resistance of the resistor 12 is 2-4 times as high as the equivalent resistance of the NMOS 3. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005184298(A) 申请公布日期 2005.07.07
申请号 JP20030420535 申请日期 2003.12.18
申请人 TOPPAN PRINTING CO LTD;TOSHIBA CORP 发明人 MATSUDA HIROYUKI;CHIN GIYOUSHIYOU;HIROSHIMA MASAHITO;HONDA YASUHIKO
分类号 H03K19/003;H03F1/56;H03K17/08;H03K17/16;H03K17/687;H03K19/0175;(IPC1-7):H03K17/16;H03K19/017 主分类号 H03K19/003
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