METHOD FOR PATH SEARCHING AND VERIFICATION

摘要

The present application describes a new path search and verification method and apparatus for identifying and selecting one or more delays for a receiver. A front-end receiver receives a signal having one or more signal images, where each signal image has a corresponding signal delay. A tree generator builds a hierarchical delay tree from a plurality of delay nodes, each corresponding to one of the signal delays. A tree searcher searches through the delay tree to identify one or more surviving delay nodes, where each surviving delay node corresponds to a candidate delay for the receiver. The receiver may also include a state machine comprising a plurality of ordered states for providing candidate delays for the receiver. The state machine stores the candidate delays and shifts the candidate delays between states within the state machine based on the latest results from the tree searcher.