发明名称 Architecture and method for parallel embedded block coding
摘要 The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720p resolution pictures at 30 fps in real time.
申请公布号 US2005135688(A1) 申请公布日期 2005.06.23
申请号 US20030739067 申请日期 2003.12.19
申请人 NATIONAL TAIWAN UNIVERSITY 发明人 CHEN LIANG-GEE;FANG HUNG-CHI;CHANG YU-WEI
分类号 G06K9/36;H04N7/26;(IPC1-7):G06K9/36 主分类号 G06K9/36
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