发明名称 |
DUAL EDGE PROGRAMMABLE DELAY UNIT |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay unit capable of shortening a delay time to a picoseconds (ps) range. <P>SOLUTION: A method and a device program a dual edge programmable delay unit that responds to an input signal with a a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust a time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust the time delay before the rise of the buffer output signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
申请公布号 |
JP2005168029(A) |
申请公布日期 |
2005.06.23 |
申请号 |
JP20040349506 |
申请日期 |
2004.12.02 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
FENG KAI D;WU HONGFEI |
分类号 |
H03K5/14;G01R1/00;H03H11/26;H03K5/00;H03K5/06;H03K5/13;H03K5/1532;H03K17/693;H03K19/0948;H03K19/173 |
主分类号 |
H03K5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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