发明名称 Bus interconnect system for graphic processing system - has individual buses coupling graphics processing elements in ring, with signal lines for transferring command signals between elements
摘要 The system includes a bus structure, coupling a number of graphics processing elements (202,222,242) in a ring. The bus structure comprises a number of individual buses (250,252,254), with each bus connecting a pair of graphics processing elements. - Each individual bus comprises a number of signal lines (250A-250F) for transferring graphics command signals and information signals between graphics processing elements in the ring.
申请公布号 DE19816153(B4) 申请公布日期 2005.06.23
申请号 DE19981016153 申请日期 1998.04.09
申请人 HEWLETT-PACKARD DEVELOPMENT CO., L.P. 发明人 FAGET, ROY R.;LARSON, RONALD D.
分类号 G06T1/20;(IPC1-7):G06F13/40;G06K11/00;G09G5/00;H04L12/40 主分类号 G06T1/20
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