| 摘要 |
PROBLEM TO BE SOLVED: To provide a sampling rate converter comprising a single phase filter not requiring a large amount of logic in which signal quality does not deteriorate after conversion and the amount of logic can be reduced sharply and easily thus realizing significant compression of logic as a whole. SOLUTION: A prestage sampler 12 samples input signals with a first sampling clock 27 having an iteration frequency of two times or more of the highest frequency of the input signal generated from a clock generating section 20. An LPF 13 limits the band of a sampled signal from the prestage sampler 12 in order to remove an aliasing distortion occurring when sampling is carried out using the output clock 28 from an output sampler 14. Since the filter circuit 13 can be constituted of a single phase FIR having no relation with the conversion phase, the structure can be simplified as compared with a conventional circuit employing a polyphase filter and the amount of logic can be reduced sharply. COPYRIGHT: (C)2005,JPO&NCIPI
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