| 发明名称 |
Method and apparatus to support an expanded register set |
| 摘要 |
Processors and methods having an expanded logical register set. In one embodiment, a processor includes Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set can include more than eight logical registers of a first type.
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| 申请公布号 |
US2005114628(A1) |
申请公布日期 |
2005.05.26 |
| 申请号 |
US20030625240 |
申请日期 |
2003.07.22 |
| 申请人 |
KAHN OPHER D.;PELEG ALEXANDER;VALENTINE BOB |
发明人 |
KAHN OPHER D.;PELEG ALEXANDER;VALENTINE BOB |
| 分类号 |
G06F9/30;G06F9/318;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
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