| 摘要 |
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC ( 640 and/or 645 ) that is part of a modulator (FIG. 6 ). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T 2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5 ). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T 2 using only a single pointer per clock cycle.
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