发明名称 Congestion control in a network device having a buffer circuit
摘要 Each packet of the present invention is assigned a priority level. The current data packet flow rate is detected. This data packet flow rate is quantized into at least one data rate level. The current buffer circuit depth is determined as is the priority associated with the current data packet. The probability that the current packet is either dropped or used is determined by using the current data packet service flow rate, the data packet priority, and the current buffer circuit depth.
申请公布号 US6898182(B1) 申请公布日期 2005.05.24
申请号 US20000620821 申请日期 2000.07.21
申请人 ARRIS INTERNATIONAL, INC 发明人 CLOONAN THOMAS J.
分类号 H04L12/56;(IPC1-7):G01R31/08;G06F11/00;G08C15/00;H04J1/16;H04J3/14 主分类号 H04L12/56
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