发明名称 |
Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios |
摘要 |
A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.
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申请公布号 |
US2005095856(A1) |
申请公布日期 |
2005.05.05 |
申请号 |
US20040963324 |
申请日期 |
2004.10.12 |
申请人 |
TU AN-CHUN;HUANG JENN-MING |
发明人 |
TU AN-CHUN;HUANG JENN-MING |
分类号 |
F28C3/08;F28D5/00;F28F25/08;(IPC1-7):H01L21/44 |
主分类号 |
F28C3/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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