| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that since the TEG (test element group) of a semiconductor integrated circuit is configured of a plurality of shift registers, and the number of terminals of inputs and outputs of the shift registers is relatively smaller than the layout size, the density of wiring is made small after carrying out placing and routing, and the failure detecting sensitivity of a wiring layer is made low as a result. SOLUTION: Wiring patterns 3a and 3b are arranged at the both sides of a wiring pattern 2 connecting the data output terminal of a flip flop and the input terminal of a flop flop in the next stage so that cell layout configuration can be realized. Furthermore, the wiring patterns 3a and 3b are connected to a power source line pattern 5a and a ground line pattern 5b. Thus, the wiring density can be made high, and sensitivity to the failure of the wiring process can be made high as a result. All the wiring patterns 3a and 3b are short-circuited, and connected to an external terminal 8. Thus, the wiring patterns can be controlled from an "L" level to an "H" level from the outside, and the failure detection rate can be increased. COPYRIGHT: (C)2005,JPO&NCIPI
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