发明名称 Fail-safe controller
摘要 A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operations; a plurality of data storage elements for storing respective results of the arithmetic and logical operations of the plurality of the processors; a comparator for comparing the results of the arithmetic and logical operations of the plurality of the processors stored in the plurality of the data storage elements; and a comparison record storage element for storing a record of the comparison results of the comparator.
申请公布号 US2005080492(A1) 申请公布日期 2005.04.14
申请号 US20040891360 申请日期 2004.07.13
申请人 HITACHI, LTD. 发明人 SHIMAMURA KOTARO;IKEDA NAOHIRO;TAKEHARA TAKESHI
分类号 G06F11/18;G05B9/03;(IPC1-7):G05B13/02 主分类号 G06F11/18
代理机构 代理人
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