发明名称 Current sample and hold circuit and method and demultiplexer and display device using the same
摘要 A data current sample and hold circuit having an input terminal of a current source type and an output terminal of a current sink type. The sample and hold circuit includes a first transistor, a capacitor, and a plurality of switches, for sampling and holding the data current sunk to an output terminal of a data driver. When the sampled and held data current is applied to the data line, the data current is sunk to an output terminal of the sample and hold circuit. The sample and hold circuit is used together with a data driver having an output terminal of the current sink type.
申请公布号 US2005073488(A1) 申请公布日期 2005.04.07
申请号 US20040954804 申请日期 2004.09.29
申请人 SHIN DONG-YONG 发明人 SHIN DONG-YONG
分类号 G09G3/20;G06G7/12;G06G7/26;G09G3/30;G09G3/32;G11C27/02;H03K17/00;H03K17/687;H03M1/12;H05B33/00;(IPC1-7):G06G7/12 主分类号 G09G3/20
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