| 摘要 |
PROBLEM TO BE SOLVED: To provide a system and a method for statistical or a probabilistic static timing analysis of a digital circuit, taking into account a statistical delay variation. SOLUTION: The delay of each gate or wire is assumed to be composed of a standard portion, a correlated random portion that is parameterized by each of sources of a variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized probability variables while taking correlations into account. Both early mode and late mode timings are included, both combinational and sequential circuits are handled, a static CMOS logic circuit in addition to a dynamic logic circuit family is made adaptable. Timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is provided as a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form. COPYRIGHT: (C)2005,JPO&NCIPI
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