METHOD OF FORMING METAL LINE IN SEMICONDUCTOR DEVICES

摘要

A method for forming a metal interconnection of a semiconductor device is provided to easily embody a micro pattern and guarantee CD(critical dimension) of a via hole and a trench pattern by greatly reducing the thickness of patterned photoresist layer by a dual damascene process using the first and second hard masks. An etch stop layer, the second insulation layer and the third insulation layer for a hard mask are sequentially formed on the first insulation layer having a lower metal interconnection. The third insulation layer is patterned and etched to form the first hard mask(18). The fourth insulation layer is formed on the resultant structure and is planarized until the first hard mask is exposed so that the second hard mask(20) is formed. The first and second hard masks are patterned, and the second insulation layer is etched to form a via hole by using the patterned first and second hard masks as an etch mask. After the first hard mask is removed, a predetermined thickness of the second insulation layer is etched to form a trench pattern by using only the residual second hard mask as an etch mask.