SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To precisely and stably synchronize a signal taken in from an external DDR-SDRAM with respect to a technique of synchronizing read data from a synchronous memory with an internal clock on the memory interface controller side.

SOLUTION: A memory interface circuit (3) can be connected to a DDR-SDRAM (6) which outputs a data strobe signal (DQS) and outputs read data (DQ) synchronously with this signal. A clock generation circuit (5) generates an internal clock signal and a memory clock signal to be supplied to the DDR-SDRAM. The memory interface circuit determines the delay of arrival of a data strobe signal relative to the internal clock signal by using the data strobe signal inputted in a read cycle to the DDR-SDRAM, samples arriving read data on the basis of a signal resulting from shifting the phase of the arriving data strobe signal and synchronizes the sampled read data with the internal clock signal on the basis of a determination result of arrival delay.

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