发明名称 DATA PROCESSING SYSTEM
摘要 The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
申请公布号 WO2005026964(A2) 申请公布日期 2005.03.24
申请号 WO2004IB51491 申请日期 2004.08.19
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;VAN DER WOLF, PIETER;VAN EIJNDHOVEN, JOSEPHUS, T., J.;BOONSTRA, JOHANNES 发明人 VAN DER WOLF, PIETER;VAN EIJNDHOVEN, JOSEPHUS, T., J.;BOONSTRA, JOHANNES
分类号 G06F12/08;G06F13/16;G06F15/173 主分类号 G06F12/08
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