| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipeline processing system which operates at high speed and consumes low power, and an information processor to which the system is applied. SOLUTION: In the case of decoding, a decoder/encoder circuit 115 accesses in parallel a first memory and a second memory in accordance with state information STO or STI and performs decoding, after storing the processed data into a tracking memory, transfers the data stored in the tracking memory to a host device 117 in response to request from the host device 117, in the case of encoding, the decoder/encoder circuit 115 writes user data transferred from the host device 117 in a block unit in a third memory as a tracking buffer and starts encoding, accesses a plurality of memories in parallel in accordance with state information STO or STI and performs decoding, and outputs to a clock generating circuit 113. COPYRIGHT: (C)2005,JPO&NCIPI
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