| 摘要 |
PROBLEM TO BE SOLVED: To increase processing speed of an information processor provided with a cache memory used by a CPU. SOLUTION: First and second memory parts 48, 49 can be set in a cache memory mode or a RAM mode independently. For example, the first memory part 48 is set in the cache memory mode, and the second memory part 49 is set in the RAM mode. In this case, the CPU 40 is connected with the second memory part 49 through an address bus 41 and a data bus 43, and the first memory part 48 is connected with a main memory 46 and a peripheral circuit 47 through an address bus 42 and a data bus 44. Therefore, the CPU40 can perform RAM access to the second memory part 49 even when the first memory part 48 is executing block transfer operation from the main memory 46. COPYRIGHT: (C)2005,JPO&NCIPI
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