| 摘要 |
1334710 Encoding/decoding digital data BURROUGHS CORP 3 Sept 1970 [17 Sept 1969] 42147/70 Headings G4C and G4A Digital data is recorded on a magnetic storage medium the significance of each bit being determined by the duration of the corresponding recorded signal and is reproduced by means of a system which includes a transducer relatively movable with respect to the storage medium, a means for computing for each bit read a period proportional to the duration of a predetermined number of preceding stored bits, and a comparator for comparing the computed prior period with the period of each signal as it is read. In an embodiment each data bit consists of a signal having two portions, a positive and a negative portion. The positive portion is of 112 Ásecs. duration and the following negative portion 112 Ásecs. for binary "0" and 188 Ásecs. for binary "1". The data is read from the storage medium and the signal is shaped into a square wave the periods Ti of which are measured. The periods of the previous two bits Ti - 1 and Ti - 2 are stored in the store 3-29 in the form: The comparator 3-27 compares the period Ti with a period B derived from the period A as described below to determine the significance of the bit corresponding to Ti. A store 3-31 contains the binary valves of the previous two bits Ti - 1 and Ti - 2. It will be seen that if the two preceding bits were 1, 1 then A=300 Ásecs., similarly for 0, 0 A = 224 Ásecs., and for 0, 1 or 10 A=262 Ásecs. In order to arrive ta a constant threshold B with which Ti is to be compared the above valves of A are multiplied by 7/6, 7/8, and 1 respectively, the multiplication being determined by the contents of store 3-31. The multiplication &c. is performed by the circuit illustrated in Fig. 5 which includes three counters 5-41, 5-43, and 5-45. Before the first data bit can be decoded it is necessary to preset the system. This may be done directly or by means of two known leader bits recorded on the storage medium. Counter 5-41 counts the clock pulse during a period Ti - 2 (the first leader bit), transfers its count to 5-43 and is reset, the transfer being by the gates 5-117. Counters 5-41 and 5-43 then both count the clock pulses occurring during a period Ti-1. The contents of counter 5-43 is then shifted left one place and transferred to 5-45 which thus contains: The contents of counter 5-45 are then counted down by the clock pulses during period Ti via a mod 7 counter 5-47 which selectively inhibits every seventh clock pulse, allows the clock pulses to pass undisturbed, or adds an additional pulse for every seven clock pulses corresponding to multiplication by 7/6, 1, and 7/8. At the end of the period Ti the ninth bit of 5-45 is interrogated to determine whether or not is has changed state thus giving an indication of the binary value given by Ti. In a further embodiment the arrangement of Fig. 5 is replaced by an analogue system, Fig. 11 (not shown). The value A is indicated by a stored charge which is compared with the charge developed during the period of the signal being read. The Specification states that the value A may be given by one or more previous bit periods other than precisely two. |
