METHOD FOR FABRICATING FLASH MEMORY DEVICE AND FLASH MEMORY DEVICE FABRICATED THEREBY TO IMPROVE UNIFORMITY OF ERASE RATE OF CELL AND DISTRIBUTION OF ERASE THRESHOLD VOLTAGE

摘要

PURPOSE: A method for fabricating a flash memory device is provided to improve uniformity of an erase rate of a cell and distribution of an erase threshold voltage by minimizing a difference of a coupling ratio of two flash memory cells formed at both sides of two bitline contact holes. CONSTITUTION: A plurality of parallel wordline patterns(314a,314b) are formed on a semiconductor substrate(300). A conformal capping layer(318) is formed on the front surface of the semiconductor substrate. The first and second interlayer dielectrics are sequentially formed on the capping layer wherein the first interlayer dielectric is made of a material layer having an isotropic etch rates faster than that of the second interlayer dielectric. The second interlayer dielectric, the first interlayer dielectric and the capping layer are patterned by an isotropic etch technique to form bitline contact holes(326) exposing the substrate between the wordline patterns wherein each bitline contact hole includes a lower bitline contact hole surrounded by the first interlayer dielectric and an upper bitline contact hole surrounded by the second interlayer dielectric. By using the capping layer as an etch stop layer, the first and second interlayer dielectrics are wet-etched to form an extended lower bitline contact hole having a greater width than that of the upper bitline contact hole.