发明名称 |
Phase error determination method and digital phase-locked loop system |
摘要 |
In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.
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申请公布号 |
US2005022076(A1) |
申请公布日期 |
2005.01.27 |
申请号 |
US20040882121 |
申请日期 |
2004.06.30 |
申请人 |
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发明人 |
NAKAMURA SHINOBU;KUDO MAMORU;OOSHIMA SATORU;YAMANE JUN;SHIMIZU HIROFUMI |
分类号 |
G11B20/14;G11B19/04;G11B27/30;H03L7/08;H03L7/085;H03L7/10;H03L7/107;H04L7/033;H04N5/935;(IPC1-7):G11B3/00;G11B5/09;H04N5/76;G11B20/10;G11B27/36;G06K5/04;G11B20/20;G11B5/00 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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