Non volatile memory array with split gate cells and method for avoiding disturbance when programming

摘要

The circuit has a table including non volatile memory cells (24A-24D), and a control logic delivering a programming voltage (VPROG) to a control gate of the cell (24A) to be programmed, through a word control line (18). A blocking logic delivers a blocking voltage (VBLOCK1) higher than the programming voltage, to the cell (24B) sharing the same line (18), through a bit control line (22) corresponding to the cell (24B). An independent claim is also included for a method of programming a memory cell of a table of an integrated circuit.