发明名称 MULTI-CHIP MODULE
摘要 <p><P>PROBLEM TO BE SOLVED: To test the quality of wiring, while reducing the number of terminals, in order to test the quality of the same. <P>SOLUTION: A selector 12a is given a test signal TDI to its input terminal A, its input terminal B is connected to the output terminal 13a of an internal logic circuit 11, and its output terminal O is connected to the input terminal 24a of an internal logic circuit 21 by way of wiring 31a. A selector 22a is connected at its input terminal A to the wiring 31a, with its input terminal B connected to the output terminal 24a of the internal logic circuit 21 and with its output terminal O connected to the signal input terminal 14a of the internal logic circuit 11 by way of wiring 32a, respectively. The selectors 12a and 22a output either of the signals given to the input terminals A and B from the output terminal O, based on a test mode signal TMS. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005017099(A) 申请公布日期 2005.01.20
申请号 JP20030182022 申请日期 2003.06.26
申请人 RENESAS TECHNOLOGY CORP 发明人 KIRITANI MASAHIDE
分类号 H01L25/04;G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 H01L25/04
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