CHIP STACK PACKAGE USING LEADFRAME OF CONVENTIONAL LOC STRUCTURE TO SIMPLIFY FABRICATING PROCESS

摘要

PURPOSE: A chip stack package is provided to simplify a fabricating process and reduce fabricating cost by fabricating a chip stack package while using a leadframe of a conventional LOC(lead on chip) structure. CONSTITUTION: A dual downset leadframe(24) includes a tip part on which a wire bonding process is performed. The first semiconductor chip(21) is attached to the lower part of the tip downset part of the leadframe. A bonding pad of the first semiconductor chip is electrically connected to the tip downset leadframe by the first metal wire(25). The second semiconductor chip(22) is attached to the upper part of the leadframe. The second semiconductor chip is electrically connected to the leadframe by the second metal wire(27). An encapsulating material(28) encapsulates the first and second semiconductor chips except the back surface of the first semiconductor chip, the first and second metal wires and a spatial region including a part of the leadframe.