发明名称 Reference voltage circuit
摘要 A reference voltage circuit includes three PMOS transistors and two NMOS transistors. The three PMOS transistors constitute a current mirror circuit and the two NMOS transistors constitute a load circuit. A dummy NMOS transistor is added to the load circuit so as to make three NMOS transistors correspond to the three PMOS transistors and a ratio of currents leaking through PN junctions of diffusion layers on the side of the current mirror circuit is set equal to a ratio of currents leaking through PN junctions of diffusion layers on the side of the load circuit. This allows the reference voltage circuit to output a reference voltage that does not change with temperature even at high temperatures.
申请公布号 US6831505(B2) 申请公布日期 2004.12.14
申请号 US20030455996 申请日期 2003.06.06
申请人 NEC CORPORATION 发明人 OZOE HIDETOSHI
分类号 G05F3/24;G05F3/26;(IPC1-7):G05F3/24 主分类号 G05F3/24
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