Secure watchdog timer

摘要

A watchdog timer including a counter, a watchdog enable mechanism, and a timeout control. The watchdog enable mechanism is set to an enabled state by receiving an enabling input and set to a disabled state only by a power cycle or a hardware reset. The timeout control is coupled to the counter and to the watchdog enable mechanism. The timeout control enables a error signal if the watchdog enable mechanism is enabled and the counter is not updated before completing a count.