发明名称 Speeded up multistage comparator with power reduction and reliable output
摘要 A configuration of sub-comparators for use within an analog to digital conversion circuit is disclosed. A number of the sub-comparators are adapted to receive equalization and power down control signals. In one embodiment, several of the sub-comparators are cascaded together in the analog to digital conversion circuit. An equalization signal and a power down control signal are applied to at least some of the sub-comparators enabling the sub-comparators to attenuate or eliminate offset voltage and environmental noise associated with the signal to be sampled. Furthermore, in accordance with another aspect, the analog to digital conversion circuit includes a latch type differential sub-comparator, which can attenuate or eliminate output levels of the sub-comparators from residing in an unstable input region of the digital converter.
申请公布号 US2004246030(A1) 申请公布日期 2004.12.09
申请号 US20030456828 申请日期 2003.06.06
申请人 YANG STEVEN JYH-REN 发明人 YANG STEVEN JYH-REN
分类号 G01R19/00;H03K3/356;H03K5/153;H03K5/24;(IPC1-7):H03K5/153 主分类号 G01R19/00
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